The present invention relates to a semiconductor device, and more specifically, to a flash memory having high coupling ratio and the method of fabricating the nonvolatile memory.
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device. The high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Further, it can be used to replace magnetic disk memory. The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), EEPROM (electrically erasable programmable read only memory), EEPROM-EAROMs and non-volatile SRAMs.
Different types of devices have been developed for specific applications requirements in each of the segments of memory. In the device, electrical alterability is achieved by Fowler-Nordheim tunneling which is cold electron tunneling through the energy barrier at a silicon-thin dielectric interface and into the oxide conduction band. Typically, the thin dielectric layer is composed of silicon dioxide and the thin silicon dioxide layer allows charges to tunnel through when a voltage is applied to the gate. These charges are trapped in the silicon dioxide and remain trapped there since the materials are high quality insulators. A conventional flash memory is a type of erasable programmable read-only memory (EPROM) One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, the speed of memory erasure is fast. For other EPROM, the memory erasure can take up to several minutes due to the erase mode of such type memory is done by bit-by-bit.
Various flash memories have been disclosed in the prior art, the type of the flash includes separated-gate and stacked-gate structure. U.S. Pat. No. 6,180,454 to Chang, et al, entitled xe2x80x9cMethod for forming flash memory devicesxe2x80x9d, was filed on Oct. 29, 1999. A further U.S. Pat. No. 6,153,906 to Chang, was filed on Dec. 8, 1998. The device includes an oxide layer on a substrate. A stacked gate is formed on the substrate. A tunnel diffusion region is formed in the substrate next to a first side of the stacked gate. The tunnel diffusion region extends to a portion of the substrate under the stacked gate. A doped region is formed in the substrate next to a second side of the stacked gate. The doped region is distant away from the stacked gate by a lateral distance. U.S. Pat. No. 5,956,268 discloses a Nonvolatile memory structure. The prior art allows for array, block erase capabilities.
U.S. Pat. No. 6,153,494 to Hsieh, et al., entitled xe2x80x9cMethod to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flashxe2x80x9d was filed on Feb. 11, 1998. The object of this invention is to provide a method of forming a stacked-gate flash memory having a shallow trench isolation with a high-step in order to increase the lateral coupling between the word line and the floating gate. Hsieh disclosed a step of forming a nitride layer and then forming a shallow trench isolation (STI) structure through the nitride layer into the substrate. Then, after oxide is filled into the STI, the nitride is then removed leaving behind a deep opening about the filled STI. The detailed description may refer to the prior art. A stacked-gate flash memory cell is provided having a shallow trench isolation with a high-step of oxide and high lateral coupling.
Hemispherical grain silicon (HSG-Si) is a silicon layer with a rough surface to increase surface area. It has been applied in the field of DRAM. For example, see the article entitled xe2x80x9cA Capacitor-Over-Bit-Line Cell with a Hemispherical Grain Storage Node For 64 Mb Dramsxe2x80x9d, IEDM Tech Dig., December 1990, pp 655-658). The HSG-Si is deposited by a low pressure chemical vapor deposition method at the transition temperature from amorphous Si to polycrystalline Si. This memory cell provides large storage capacitance by increasing the effective surface area of a simple storage node and is manufactured by optical delineation. The HSG-Si storage node can be fabricated by addition of two process steps, i.e. HSG-Si deposition and a etchback. HSG-Si appeared on silicon surface by using a seeding method.
The object of the present invention is to form flash memory with a higher coupling ratio.
It is another object of this invention to provide a method of forming a stacked-gate flash memory having HSG-Si to increase the coupling ratio between the control gate and the floating gate of the cell.
The stacked-gate flash memory cell includes a trench formed in a substrate and a tunneling oxide is formed on the substrate. A first part of the floating gate is formed on the tunneling oxide. A raised isolation filler is formed in the trench and protrudes over the upper surface of the first part of the floating gate, thereby forming a cavity between the two adjacent raised isolation fillers. A second part of the floating gate is formed along the surface of the cavity to have a U-shaped structure in cross sectional view. A dielectric layer is conformally formed on the surface of the second part of the floating gate and a control gate is formed on the dielectric layer.
The method comprises forming a first dielectric layer on a semiconductor substrate as a tunneling dielectric and forming a first conductive layer and a sacrificial layer on the first dielectric layer. The next step is to pattern the sacrificial layer, the first dielectric layer, the first conductive layer and the substrate to form a trench in the substrate. An isolation material fills the trench, a portion of the isolation material is removed to the surface of the sacrificial layer. The sacrificial layer is then removed, thereby forming a cavity between adjacent isolation structures. A second conductive layer is formed along a surface of the cavity and the isolation structure. Next, a portion of the second conductive layer is removed to the surface of the isolation structure. Subsequently, a second dielectric layer is formed on a surface of the floating gate, and a third conductive layer is formed on the second dielectric layer as a control gate.